Parents (Total: 4)

The searched file hash is included in 4 parent files which include package known and seen by metalookup. A sample is included below:

Key	Value
FileSize	17780
MD5	6CBD745A71FDB3AFF5EEF8CD5D77F1A7
PackageDescription	Xilinx Intermediate Representation (XIR) for deep learning algorithms (develop) Xilinx Intermediate Representation (XIR) is a graph based intermediate representation of the AI algorithms which is well designed for compilation and efficient deployment of the Domain-specific Processing Unit (DPU) on the FPGA platform. Advanced users can apply Whole Application Acceleration to benefit from the power of FPGA by extending the XIR to support customized IP in Vitis AI flow. . XIR includes Op, Tensor, Graph and Subgraph libraries, which providing a clear and flexible representation for the computational graph. For now, it's the foundation for the Vitis AI quantizer, compiler, runtime and many other tools. XIR provides in-memory format, and file format for different usage. The in-memory format XIR is a Graph object, and the file format is a xmodel. A Graph object can be serialized to a xmodel while the xmodel can be deserialized to the Graph object. . In the Op library, there's a well-defined set of operators to cover the wildly used deep learning frameworks, e.g. TensorFlow, Pytorch and Caffe, and all of the built-in operators for DPU. This enhences the expression ability and achieves one of the core goals of eliminating the difference between these frameworks and providing a unified representation for users and developers. . XIR also provides a Python APIs which is named PyXIR. It enables Python users to fully access XIR and benefits in a pure Python environment, e.g. co-develop and integrate users' Python project with the current XIR based tools without massive dirty work to fix the gap between two languages. . This package provides the development environment for XIR.
PackageMaintainer	Punit Agrawal <punit@debian.org>
PackageName	libxir-dev
PackageSection	libdevel
PackageVersion	1.4-1
SHA-1	E06549795FB614B3B0555275202F0A37F48D1ABB
SHA-256	9E8CE57F35ECFA912F906E672437205C9A95A965C0E81890CFCCB558B2D16D38

Key	Value
FileSize	17784
MD5	F495DEA2EF315F714778A5DB2BBB1C5B
PackageDescription	Xilinx Intermediate Representation (XIR) for deep learning algorithms (develop) Xilinx Intermediate Representation (XIR) is a graph based intermediate representation of the AI algorithms which is well designed for compilation and efficient deployment of the Domain-specific Processing Unit (DPU) on the FPGA platform. Advanced users can apply Whole Application Acceleration to benefit from the power of FPGA by extending the XIR to support customized IP in Vitis AI flow. . XIR includes Op, Tensor, Graph and Subgraph libraries, which providing a clear and flexible representation for the computational graph. For now, it's the foundation for the Vitis AI quantizer, compiler, runtime and many other tools. XIR provides in-memory format, and file format for different usage. The in-memory format XIR is a Graph object, and the file format is a xmodel. A Graph object can be serialized to a xmodel while the xmodel can be deserialized to the Graph object. . In the Op library, there's a well-defined set of operators to cover the wildly used deep learning frameworks, e.g. TensorFlow, Pytorch and Caffe, and all of the built-in operators for DPU. This enhences the expression ability and achieves one of the core goals of eliminating the difference between these frameworks and providing a unified representation for users and developers. . XIR also provides a Python APIs which is named PyXIR. It enables Python users to fully access XIR and benefits in a pure Python environment, e.g. co-develop and integrate users' Python project with the current XIR based tools without massive dirty work to fix the gap between two languages. . This package provides the development environment for XIR.
PackageMaintainer	Punit Agrawal <punit@debian.org>
PackageName	libxir-dev
PackageSection	libdevel
PackageVersion	1.4-1
SHA-1	71CAAD514F16B585AECA7FD835365F9B07C14589
SHA-256	3B69F59FFBDADA50346035841C72EC04FC79F8228C29B0028BF518FF81985A90

Key	Value
FileSize	17780
MD5	88C9A20600F39D062C5079AE08057D8B
PackageDescription	Xilinx Intermediate Representation (XIR) for deep learning algorithms (develop) Xilinx Intermediate Representation (XIR) is a graph based intermediate representation of the AI algorithms which is well designed for compilation and efficient deployment of the Domain-specific Processing Unit (DPU) on the FPGA platform. Advanced users can apply Whole Application Acceleration to benefit from the power of FPGA by extending the XIR to support customized IP in Vitis AI flow. . XIR includes Op, Tensor, Graph and Subgraph libraries, which providing a clear and flexible representation for the computational graph. For now, it's the foundation for the Vitis AI quantizer, compiler, runtime and many other tools. XIR provides in-memory format, and file format for different usage. The in-memory format XIR is a Graph object, and the file format is a xmodel. A Graph object can be serialized to a xmodel while the xmodel can be deserialized to the Graph object. . In the Op library, there's a well-defined set of operators to cover the wildly used deep learning frameworks, e.g. TensorFlow, Pytorch and Caffe, and all of the built-in operators for DPU. This enhences the expression ability and achieves one of the core goals of eliminating the difference between these frameworks and providing a unified representation for users and developers. . XIR also provides a Python APIs which is named PyXIR. It enables Python users to fully access XIR and benefits in a pure Python environment, e.g. co-develop and integrate users' Python project with the current XIR based tools without massive dirty work to fix the gap between two languages. . This package provides the development environment for XIR.
PackageMaintainer	Punit Agrawal <punit@debian.org>
PackageName	libxir-dev
PackageSection	libdevel
PackageVersion	1.4-1
SHA-1	EAFA2210DB1574B4A819219B5073C852B7B5C448
SHA-256	BD35110F67DE170B0E02860B6942AD28ADD2F8D5B51FD983F8BA9E06C4EE7FC2

Key	Value
FileSize	17792
MD5	34448452CD36D29A180283B5674B9C10
PackageDescription	Xilinx Intermediate Representation (XIR) for deep learning algorithms (develop) Xilinx Intermediate Representation (XIR) is a graph based intermediate representation of the AI algorithms which is well designed for compilation and efficient deployment of the Domain-specific Processing Unit (DPU) on the FPGA platform. Advanced users can apply Whole Application Acceleration to benefit from the power of FPGA by extending the XIR to support customized IP in Vitis AI flow. . XIR includes Op, Tensor, Graph and Subgraph libraries, which providing a clear and flexible representation for the computational graph. For now, it's the foundation for the Vitis AI quantizer, compiler, runtime and many other tools. XIR provides in-memory format, and file format for different usage. The in-memory format XIR is a Graph object, and the file format is a xmodel. A Graph object can be serialized to a xmodel while the xmodel can be deserialized to the Graph object. . In the Op library, there's a well-defined set of operators to cover the wildly used deep learning frameworks, e.g. TensorFlow, Pytorch and Caffe, and all of the built-in operators for DPU. This enhences the expression ability and achieves one of the core goals of eliminating the difference between these frameworks and providing a unified representation for users and developers. . XIR also provides a Python APIs which is named PyXIR. It enables Python users to fully access XIR and benefits in a pure Python environment, e.g. co-develop and integrate users' Python project with the current XIR based tools without massive dirty work to fix the gap between two languages. . This package provides the development environment for XIR.
PackageMaintainer	Punit Agrawal <punit@debian.org>
PackageName	libxir-dev
PackageSection	libdevel
PackageVersion	1.4-1
SHA-1	F885C353E29C716A972B96AE0DA9059D51D48F47
SHA-256	F56447C4F86D5E5110315893313648889917A793E6DBACA8F04BE70D820F5D00