| PackageDescription | Xilinx Intermediate Representation (XIR) for deep learning algorithms (develop)
Xilinx Intermediate Representation (XIR) is a graph based
intermediate representation of the AI algorithms which is well
designed for compilation and efficient deployment of the
Domain-specific Processing Unit (DPU) on the FPGA platform. Advanced
users can apply Whole Application Acceleration to benefit from the
power of FPGA by extending the XIR to support customized IP in Vitis
AI flow.
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XIR includes Op, Tensor, Graph and Subgraph libraries, which
providing a clear and flexible representation for the computational
graph. For now, it's the foundation for the Vitis AI quantizer,
compiler, runtime and many other tools. XIR provides in-memory
format, and file format for different usage. The in-memory format XIR
is a Graph object, and the file format is a xmodel. A Graph object
can be serialized to a xmodel while the xmodel can be deserialized to
the Graph object.
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In the Op library, there's a well-defined set of operators to cover
the wildly used deep learning frameworks, e.g. TensorFlow, Pytorch
and Caffe, and all of the built-in operators for DPU. This enhences
the expression ability and achieves one of the core goals of
eliminating the difference between these frameworks and providing a
unified representation for users and developers.
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XIR also provides a Python APIs which is named PyXIR. It enables
Python users to fully access XIR and benefits in a pure Python
environment, e.g. co-develop and integrate users' Python project with
the current XIR based tools without massive dirty work to fix the gap
between two languages.
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This package provides the development environment for XIR. |