Result for 256159DA8F56F043114244DDD64403557E02AAAB

Query result

Key Value
FileName./usr/share/doc/packages/perl-Perlilog/examples/ex3/PLverilog/test.v
FileSize1961
MD56F2CB3CCC3FDA70CE7F166791A90A3B2
SHA-1256159DA8F56F043114244DDD64403557E02AAAB
SHA-256E6DE9B517DEAED1E0A21FE35856EEEC7D9B8FD3B144C2A1FDBBCCE0709724BEB
SSDEEP24:EBdIoWePkEorPEU364B9gVTJ4LEwWEJK5sFBbL3+Uk93S3cTbbol+zPg1W9Bq4ey:EBdIRDrq9H4NhVk9mcT2h1W9k4ey
TLSHT14E41CD1E9153C09315B1C470EB20CD46C66A943B846703DDFB4EB0938FB004EAF786E2
hashlookup:parent-total1
hashlookup:trust55

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Parents (Total: 1)

The searched file hash is included in 1 parent files which include package known and seen by metalookup. A sample is included below:

Key Value
MD556B39BEF0E68A12DB7A8114C2BF8DD68
PackageArchnoarch
PackageDescriptionThe project is extensively documented in Perlilog's user guide, which can be downloaded at http://www.billauer.co.il/perlilog.html. In wide terms, Perlilog is a Perl environment for Verilog code manipulation. It supplies the Perl programmer with several strong tools for managing Perl modules and connecting between them. Originally, Perlilog was intended for integration of Verilog IP cores, but it's useful for the following tasks as well: * Scripts that generate Verilog code automatically * "Hook-up" of modules: Assigning pins, connecting to ASIC pads, etc. * Automatic generation of buses and bus controllers, with a variable number of members and parametrized arbitration rules * Automatic generation of bridges when needed to interface between different bus protocols
PackageNameperl-Perlilog
PackageRelease1.61
PackageVersion1.0
SHA-1C8650A814B34295711288BC07A5FBE8ECA50A235
SHA-256EF7820F25F062E5CF38CFF36FF4EDCCC69B09062BFAB276AD47FE9A583FCEEA4