Parents (Total: 101)
The searched file hash is included in 101 parent files which include package known and seen by metalookup. A sample is included below:
Key |
Value |
MD5 | 6AC79349FF3322A81DEBAA93293D728F |
PackageArch | s390x |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageMaintainer | Fedora Project |
PackageName | iverilog |
PackageRelease | 2.fc19 |
PackageVersion | 0.9.20120609 |
SHA-1 | 02E3BD449B812230F7899D570C830CBC85F23002 |
SHA-256 | A9AAFD6575E0A79F6B99DACD507789979321B62B83EDD4F4A52CFB00ECFAE020 |
Key |
Value |
MD5 | 28F8F2D7B90402C8E2DE909B8B5CB3B2 |
PackageArch | armv5tel |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageMaintainer | Fedora Project |
PackageName | iverilog |
PackageRelease | 4.fc18 |
PackageVersion | 0.9.20111101 |
SHA-1 | 041E56FB924F3E213BB1FD35C8EF48E4650785AE |
SHA-256 | 21FA837D987322DC60E452812DF8F545079A45F739F40830574B0C98E59C7238 |
Key |
Value |
MD5 | E8AB98EE8F8C854A953E0C95D9DB1634 |
PackageArch | i586 |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard and supports a subset of the IEEE-1800
standard. |
PackageMaintainer | umeabot <umeabot> |
PackageName | iverilog |
PackageRelease | 2.mga9 |
PackageVersion | 11.0 |
SHA-1 | 0A33F7BC7AD7C35AE4104C75CC476D89FAC50096 |
SHA-256 | 41425B53D2FFAF8C934CE2CF777CB901E96A94779511504B5A15C2C0450E5C22 |
Key |
Value |
MD5 | E40453F93D19EAD589D494C442F70E32 |
PackageArch | x86_64 |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageMaintainer | Fedora Project |
PackageName | iverilog |
PackageRelease | 2.el7 |
PackageVersion | 10_2 |
SHA-1 | 0B0A919417F8A5170B2EA1F9BF5808C8976EF372 |
SHA-256 | 0775DF03AC9EE3871458561E38526E73650A14E2F4C0268910F4408270D71D66 |
Key |
Value |
MD5 | D099CEDE5A8B38987A75A04D88BB1F0F |
PackageArch | x86_64 |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageMaintainer | https://bugs.opensuse.org |
PackageName | iverilog |
PackageRelease | bp155.2.10 |
PackageVersion | 10.1 |
SHA-1 | 0EDFF8ABD1AE185FC9AD75320BD6910AAF509669 |
SHA-256 | 22A8E670A1B51FD2545E6909381A31A9C767E885CEA286DECB4749E817C2DA4C |
Key |
Value |
MD5 | AAAB7580C2586E27D653840F9ECBAABC |
PackageArch | x86_64 |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageMaintainer | Fedora Project |
PackageName | iverilog |
PackageRelease | 2.fc34 |
PackageVersion | 11.0 |
SHA-1 | 1006410C9F8DC95D2CF4B090D500AC1C5F904F07 |
SHA-256 | B7F275D11D89758B589DF4F44006AD0970444911C7C29AC5929DE05227DC30D0 |
Key |
Value |
MD5 | 010DA9EBF323A1C5F96E39262FA11D77 |
PackageArch | aarch64 |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard and supports a subset of the IEEE-1800
standard. |
PackageMaintainer | martinw <martinw> |
PackageName | iverilog |
PackageRelease | 1.mga8 |
PackageVersion | 11.0 |
SHA-1 | 1EC321C6BD93A2D30C97CB594F158B7D44258D63 |
SHA-256 | E5F405C516B9C511D8B6EC520BA6A6E622CE197620F97E4F3AEDF5643D0B7E48 |
Key |
Value |
MD5 | 7E23400D30E01B2AA5EEF9F666A3A7AF |
PackageArch | s390 |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageMaintainer | Fedora Project |
PackageName | iverilog |
PackageRelease | 5.fc21 |
PackageVersion | 0.9.20120609 |
SHA-1 | 21BD154B6CF4E4A640D3927D6C93F1EE2EE8C8BD |
SHA-256 | C5D2F6E04D32F72A0850EBDE8B6D66125060CECF6E0E5B5C8E50BFAB66887B55 |
Key |
Value |
MD5 | 37F92897BB6B49889FD589E9E3150C2F |
PackageArch | sparcv9 |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageMaintainer | Fedora Project |
PackageName | iverilog |
PackageRelease | 6.fc12 |
PackageVersion | 0.9.20090423 |
SHA-1 | 22A6FE08D7FA5D5F9096234A350AD14696C95A7F |
SHA-256 | 3C5D6740994B128B5300DD15847F7700C66A5CF338A99A33E77267ABF798B048 |
Key |
Value |
MD5 | 49E5BC27819930831A0D8655DB6FA3FD |
PackageArch | x86_64 |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageName | iverilog |
PackageRelease | lp152.8.1 |
PackageVersion | 11.0 |
SHA-1 | 22B86E7655D145CC1FD4D19CB7628D831ABF34BC |
SHA-256 | 361EFE48A50C8A479AE3CA26E10875622F9A9708AC5A5D687FAE849E9264A369 |