Parents (Total: 155)

The searched file hash is included in 155 parent files which include package known and seen by metalookup. A sample is included below:

Key	Value
FileSize	1913142
MD5	ED0C5FC895E8FA3A42A56CAF07A4F8A6
PackageDescription	Icarus verilog compiler Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs. . The compiler can target either simulation, or netlist (EDIF).
PackageMaintainer	Debian Electronics Team <pkg-electronics-devel@lists.alioth.debian.org>
PackageName	iverilog
PackageSection	electronics
PackageVersion	10.1-0.1+b2
SHA-1	024FD8503D89B6B0D09C91A2507D7D9266C4CB95
SHA-256	F7EC9C3AC27A5C1DEF6A4E9F1D337E40592FEB0DA1CFEC0B0420D57D1023A74D

Key	Value
FileName	https://ftp.lysator.liu.se/pub/OpenBSD/6.1/packages//powerpc//iverilog-10.1.1.tgz
MD5	BBEB90F4E8AA2D156BF2D08DB684D872
SHA-1	040299E9A50FF067B25F9CEC4FE2E203319E8080
SHA-256	32015D37B536F91E9790DD0FDB61BFE8B570313696DA536DB2CEC0E792A69AEE
SSDEEP	49152:uzO3L2QuD61xzNz+L7VAMaP6Sr6WvZh5NBnwVn+99VZbAWRGOWD:h1NNz+L7V2yTWvZbnwV69V++jWD
TLSH	T1DDC5336C17216FAABB6EECBCBC9725647004C640FCF07D8127E2ABDB5612987C51FA44

Key	Value
FileName	https://ftp.lysator.liu.se/pub/OpenBSD/6.2/packages//hppa//iverilog-10.1.1p0.tgz
MD5	5EB8861579E84B3C96CD144F277ABCE6
SHA-1	08C68B1A426A2538F0F1A67FD498F760E3A5E82B
SHA-256	64D21BAC15C7DD523205305E1727E6918DA8A1DB449424315D7DFF75D916C8DA
SSDEEP	49152:e168dI0Pw4QoiHQPEBjWi9QRcCTILRXDN6Ym3NV2n8bHEf/934FYrSq1vFWD:e168dIew1zSEdQRcRXDs3j2n8o/93YRD
TLSH	T196D533064C2FCE30D4CEF62A065CC2223B6279ED93D749E160E4A92597876E13378F97

Key	Value
FileName	https://ftp.lysator.liu.se/pub/OpenBSD/6.1/packages//arm//iverilog-10.1.1.tgz
MD5	2C8BB71C704C0C8DFA7AF1128D6282E1
SHA-1	09DAE8480845915B728A3910D03992A48AA9DF32
SHA-256	D4881F30C961E63A3D6BE82869B63F60459C3720D4554FD9091F3494EC64FB68
SSDEEP	49152:UF+aTP5TLytDNUllZOBJeOpSJPTY9bOr5pC0dMUYadIWkx:KTtgNUl/iJ1kJPTYajqUYaSWkx
TLSH	T1C4B5330021054E2EB65D4673CEA22C3D5EF3CBAB16298C0F1E19D182BD1A777B6379B5

Key	Value
MD5	E8AB98EE8F8C854A953E0C95D9DB1634
PackageArch	i586
PackageDescription	Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard and supports a subset of the IEEE-1800 standard.
PackageMaintainer	umeabot <umeabot>
PackageName	iverilog
PackageRelease	2.mga9
PackageVersion	11.0
SHA-1	0A33F7BC7AD7C35AE4104C75CC476D89FAC50096
SHA-256	41425B53D2FFAF8C934CE2CF777CB901E96A94779511504B5A15C2C0450E5C22

Key	Value
MD5	E40453F93D19EAD589D494C442F70E32
PackageArch	x86_64
PackageDescription	Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.
PackageMaintainer	Fedora Project
PackageName	iverilog
PackageRelease	2.el7
PackageVersion	10_2
SHA-1	0B0A919417F8A5170B2EA1F9BF5808C8976EF372
SHA-256	0775DF03AC9EE3871458561E38526E73650A14E2F4C0268910F4408270D71D66

Key	Value
FileName	http://dl-cdn.alpinelinux.org/alpine/latest-stable//community//x86_64//iverilog-12.0-r1.apk
MD5	7F327A4B9708D12CACCFB3E75721E1F7
SHA-1	0BAC5C592B8C3A6604C6E66D025BD6BEC7D37FB5
SHA-256	E2D87993C997BEFECBB04E2FB11167327B14CFD3A75D544FA7F8A5E5F090B80D
SSDEEP	24576:XeO+Ck87dfIHKZQ4Xb8g4fumf+6R5ZqYeHoeafroSesJa6bFKmwU4H1kBTdkAAS7:hdPxfIyoghJ6Zne3a8SjUrekSEp5WJom
TLSH	T1299533BE3FB60A12987F645EF1B25977CF2E91F39D06844A50F4F14E8A509202F9CD68

Key	Value
MD5	D099CEDE5A8B38987A75A04D88BB1F0F
PackageArch	x86_64
PackageDescription	Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.
PackageMaintainer	https://bugs.opensuse.org
PackageName	iverilog
PackageRelease	bp155.2.10
PackageVersion	10.1
SHA-1	0EDFF8ABD1AE185FC9AD75320BD6910AAF509669
SHA-256	22A8E670A1B51FD2545E6909381A31A9C767E885CEA286DECB4749E817C2DA4C

Key	Value
MD5	AAAB7580C2586E27D653840F9ECBAABC
PackageArch	x86_64
PackageDescription	Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.
PackageMaintainer	Fedora Project
PackageName	iverilog
PackageRelease	2.fc34
PackageVersion	11.0
SHA-1	1006410C9F8DC95D2CF4B090D500AC1C5F904F07
SHA-256	B7F275D11D89758B589DF4F44006AD0970444911C7C29AC5929DE05227DC30D0

Key	Value
FileName	https://ftp.lysator.liu.se/pub/OpenBSD/6.5/packages//powerpc//iverilog-10.2p1.tgz
MD5	B6EF6583AC9C1890F766E864E10BF2F2
SHA-1	1051AAE315B29ED28DB5158D2CA4AADF4A642B43
SHA-256	E9B94B2191DA0ECA98844C8192DA58DBEEF0F47994061BB3C1449A20CA9D9365
SSDEEP	49152:KMCuJXti8qX40M73qQmHLj98JXUaMXS+ca1RGlcLywjI58ygVroO5/QsYlWD:7CwiZX40M73qRrhNaMXSjaLmyy8I7Qrj
TLSH	T13FC5336F9D1547CE3FCC51CAC85F99FB323605876A001A09466C856ACF88ED3BBB4972