Parents (Total: 7)

The searched file hash is included in 7 parent files which include package known and seen by metalookup. A sample is included below:

Key	Value
MD5	681070AD15047B67920E26D5DC4BDB46
PackageArch	armv7hl
PackageDescription	Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
PackageMaintainer	Fedora Project
PackageName	verilator
PackageRelease	1.fc32
PackageVersion	4.028
SHA-1	1026ACCA8F7A826650B07F3C1E75DFEE90B23AB1
SHA-256	68E5D5ED9FB98D6FE62EC81160E235F929C563BD68B9873D36616B4BC8401315

Key	Value
MD5	7BEA42A9770A11E067019E6CA5CE9AEC
PackageArch	x86_64
PackageDescription	Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
PackageMaintainer	Fedora Project
PackageName	verilator
PackageRelease	1.el8
PackageVersion	4.028
SHA-1	C8F3D05415CEB41AB795F2E20D0441EA65883596
SHA-256	C80D6274DA2765184A6F398BC3D14D143EE444C2C59B278AEA9D9177E64D3330

Key	Value
MD5	70925E2A474E9C2CCBB91A809762A593
PackageArch	s390x
PackageDescription	Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
PackageMaintainer	Fedora Project
PackageName	verilator
PackageRelease	1.el8
PackageVersion	4.028
SHA-1	1544579E1BE22CC7C9C2AA1050D9C6422C1F69A5
SHA-256	4CDAC7DA2A62ACA33EFBAE8A8C9E43A27297DE4ADA937E6719C444C0CF607E42

Key	Value
MD5	BA9CF39CA5071BE93FA46C6E4B85C0AB
PackageArch	x86_64
PackageDescription	Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
PackageMaintainer	Fedora Project
PackageName	verilator
PackageRelease	1.fc32
PackageVersion	4.028
SHA-1	C9F2AA67B8453EF6086C93F10631C4C159A52ED3
SHA-256	7CAF38886071AE8794DA54B66A4C57D828D1C06BB7B44C1EFA71A0CF53591A99

Key	Value
MD5	6140166DC82CA56269157D8EB9A74B01
PackageArch	aarch64
PackageDescription	Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
PackageMaintainer	Fedora Project
PackageName	verilator
PackageRelease	1.fc32
PackageVersion	4.028
SHA-1	91444EC89342DA306F7D07A3CD2E0BF2AC00AC9A
SHA-256	4C9731AC2E5A963F2839C9F52F6934C61A351EE16D459D5D7F2CECD00C5B5F4E

Key	Value
MD5	E6144312AF05C4BC547A73C996405257
PackageArch	ppc64le
PackageDescription	Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
PackageMaintainer	Fedora Project
PackageName	verilator
PackageRelease	1.el8
PackageVersion	4.028
SHA-1	C071EB6AC42AACC7EF5FB6BD4E73C7D4C36F047E
SHA-256	B13A29E2CCE2FDD3FC12B7DB4E6EB5ABFD4E0ED4E44A7F2641270B4763EAE775

Key	Value
MD5	E12461904F9B77E25C5F7123E1C6F9E8
PackageArch	aarch64
PackageDescription	Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
PackageMaintainer	Fedora Project
PackageName	verilator
PackageRelease	1.el8
PackageVersion	4.028
SHA-1	1AF38B5EEA84B69408C63D9EEBF7D08A12A6F6CE
SHA-256	EA4149B40ECF6510A264E29324A5DBD8DACFFECC8C10C6DEC0DD5648902C1482