Parents (Total: 8)
The searched file hash is included in 8 parent files which include package known and seen by metalookup. A sample is included below:
Key |
Value |
MD5 | 29F2F9D412EDDD3D917A4FBECDD6951F |
PackageArch | armv7hl |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageMaintainer | Fedora Project |
PackageName | iverilog |
PackageRelease | 4.fc33 |
PackageVersion | 10.3 |
SHA-1 | DDA94A6BF471ED8E1008465158F5D896C12D14B0 |
SHA-256 | 1C917DF5680E7B8DAA6D353AA3E33C94A5A01C2036EE0370A3800752E4F759B1 |
Key |
Value |
MD5 | 3A866F3CD57B207082CD57B818110E49 |
PackageArch | aarch64 |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageMaintainer | Fedora Project |
PackageName | iverilog |
PackageRelease | 4.fc33 |
PackageVersion | 10.3 |
SHA-1 | 6C15A51A58BEAB0DFC479B07D69768E5AD5FF9E0 |
SHA-256 | 8381649AB7CE5E6DAFC28A160B421F24A84516B739296F03C3F43889EFB50AF7 |
Key |
Value |
FileSize | 1858972 |
MD5 | CF1A92BFA91AF76CFF194E34DCB5B74E |
PackageDescription | Icarus verilog compiler
Icarus Verilog is intended to compile all of the Verilog HDL as
described in the IEEE-1364 standard. It is not quite there
yet. It does currently handle a mix of structural and behavioral
constructs.
.
The compiler can target either simulation, or netlist (EDIF). |
PackageMaintainer | Ubuntu Developers <ubuntu-devel-discuss@lists.ubuntu.com> |
PackageName | iverilog |
PackageSection | electronics |
PackageVersion | 10.3-1build1 |
SHA-1 | 1C8067559FF7088BD7D8EFCEB11DE11823768F1B |
SHA-256 | B609858C6338F6EF459D5599F0DED8088B517901C093204D32105814661767AF |
Key |
Value |
MD5 | F28CB6AE18F2696CCB9425E312A2AB42 |
PackageArch | x86_64 |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageMaintainer | Fedora Project |
PackageName | iverilog |
PackageRelease | 1.fc32 |
PackageVersion | 10.3 |
SHA-1 | 475AC2F5E40D42EC16B8AE949D0314B8217556C2 |
SHA-256 | 14B22192EF5B68EFF0E3FD796E783BDCBD42636D2BD5F54329B34C686FE4C92E |
Key |
Value |
MD5 | 40CA8D81770FEC6A83B8B1A797673172 |
PackageArch | x86_64 |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageMaintainer | Fedora Project |
PackageName | iverilog |
PackageRelease | 4.fc33 |
PackageVersion | 10.3 |
SHA-1 | 7F9DDFF1853A1F864A4A8D834FB446B8EA1B1E15 |
SHA-256 | 05C7660621EF5DC14E19FD9996A7C9C503D1682C3E88B7544361CC7C5C397225 |
Key |
Value |
FileSize | 1860936 |
MD5 | B10C05F95E561EBE1DA8E79D8B9D423A |
PackageDescription | Icarus verilog compiler
Icarus Verilog is intended to compile all of the Verilog HDL as
described in the IEEE-1364 standard. It is not quite there
yet. It does currently handle a mix of structural and behavioral
constructs.
.
The compiler can target either simulation, or netlist (EDIF). |
PackageMaintainer | Ubuntu Developers <ubuntu-devel-discuss@lists.ubuntu.com> |
PackageName | iverilog |
PackageSection | electronics |
PackageVersion | 10.3-2 |
SHA-1 | D18188440AFB044159A32836CA18B809C3B7CEEE |
SHA-256 | 3768B658606C8C6D9E6C09A4561D49C712C5D032F59BB1BB341727932B0FF866 |
Key |
Value |
MD5 | C0116B97A1FE5F29C62A45BE334B0D48 |
PackageArch | armv7hl |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageMaintainer | Fedora Project |
PackageName | iverilog |
PackageRelease | 1.fc32 |
PackageVersion | 10.3 |
SHA-1 | 947B4DD5736218746A8EB03FAFC110679C7A4DF8 |
SHA-256 | BD292BBD2AA7F038CB32E0CAD9624321F15489503A558C86F6D09304836D2970 |
Key |
Value |
MD5 | 251184D0C8049F9150176DC1FFB5E8FC |
PackageArch | aarch64 |
PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
PackageMaintainer | Fedora Project |
PackageName | iverilog |
PackageRelease | 1.fc32 |
PackageVersion | 10.3 |
SHA-1 | 30F34AAA5D901735102D92C84A87979FF28B99F3 |
SHA-256 | 551603F8AD8862E17297667AE18B0D08B2E6DC161B60E7BA2A8CFD286FCFF2AF |