Result for 0AFAFB7F69826718E67E26A6327F8973110F4749

Query result

Key Value
FileName./usr/share/man/man1/verilator.1.gz
FileSize70208
MD5A867B14FC88FCAA26925047136739DB2
SHA-10AFAFB7F69826718E67E26A6327F8973110F4749
SHA-25630EA26B4C6FF43D8D0FF0E709E4BCBB35E386404D412341E6D5306F09B8A1BEA
SSDEEP1536:qcy7IGxXUzaMVSSjn8dGUzTAzX5QTZ9lb1BZqMx:UDUaU8dfXAmBd
TLSHT19C6312A4E07DB352124D5F87035DA9105A508CBEEE300ADC8DBAAED06D76C85FCD49B9
hashlookup:parent-total3
hashlookup:trust65

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Parents (Total: 3)

The searched file hash is included in 3 parent files which include package known and seen by metalookup. A sample is included below:

Key Value
MD5681070AD15047B67920E26D5DC4BDB46
PackageArcharmv7hl
PackageDescriptionVerilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
PackageMaintainerFedora Project
PackageNameverilator
PackageRelease1.fc32
PackageVersion4.028
SHA-11026ACCA8F7A826650B07F3C1E75DFEE90B23AB1
SHA-25668E5D5ED9FB98D6FE62EC81160E235F929C563BD68B9873D36616B4BC8401315
Key Value
MD5BA9CF39CA5071BE93FA46C6E4B85C0AB
PackageArchx86_64
PackageDescriptionVerilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
PackageMaintainerFedora Project
PackageNameverilator
PackageRelease1.fc32
PackageVersion4.028
SHA-1C9F2AA67B8453EF6086C93F10631C4C159A52ED3
SHA-2567CAF38886071AE8794DA54B66A4C57D828D1C06BB7B44C1EFA71A0CF53591A99
Key Value
MD56140166DC82CA56269157D8EB9A74B01
PackageArchaarch64
PackageDescriptionVerilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
PackageMaintainerFedora Project
PackageNameverilator
PackageRelease1.fc32
PackageVersion4.028
SHA-191444EC89342DA306F7D07A3CD2E0BF2AC00AC9A
SHA-2564C9731AC2E5A963F2839C9F52F6934C61A351EE16D459D5D7F2CECD00C5B5F4E