Parents (Total: 65)
The searched file hash is included in 65 parent files which include package known and seen by metalookup. A sample is included below:
| Key |
Value |
| MD5 | 6AC79349FF3322A81DEBAA93293D728F |
| PackageArch | s390x |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | Fedora Project |
| PackageName | iverilog |
| PackageRelease | 2.fc19 |
| PackageVersion | 0.9.20120609 |
| SHA-1 | 02E3BD449B812230F7899D570C830CBC85F23002 |
| SHA-256 | A9AAFD6575E0A79F6B99DACD507789979321B62B83EDD4F4A52CFB00ECFAE020 |
| Key |
Value |
| MD5 | 28F8F2D7B90402C8E2DE909B8B5CB3B2 |
| PackageArch | armv5tel |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | Fedora Project |
| PackageName | iverilog |
| PackageRelease | 4.fc18 |
| PackageVersion | 0.9.20111101 |
| SHA-1 | 041E56FB924F3E213BB1FD35C8EF48E4650785AE |
| SHA-256 | 21FA837D987322DC60E452812DF8F545079A45F739F40830574B0C98E59C7238 |
| Key |
Value |
| MD5 | 55B665E6EFD03CE15A47BFE34C6FB06B |
| PackageArch | i386 |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | Fedora Project <http://bugzilla.redhat.com/bugzilla> |
| PackageName | iverilog |
| PackageRelease | 1.el4 |
| PackageVersion | 0.9.20070608 |
| SHA-1 | 20FCDCECB1A2625E3ED996A36B48AC1B1217272A |
| SHA-256 | 35946DF89AD4FE0C1741802D5D76D4793A17FD1BE5257D3C9C67E8F2AF785531 |
| Key |
Value |
| MD5 | 7E23400D30E01B2AA5EEF9F666A3A7AF |
| PackageArch | s390 |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | Fedora Project |
| PackageName | iverilog |
| PackageRelease | 5.fc21 |
| PackageVersion | 0.9.20120609 |
| SHA-1 | 21BD154B6CF4E4A640D3927D6C93F1EE2EE8C8BD |
| SHA-256 | C5D2F6E04D32F72A0850EBDE8B6D66125060CECF6E0E5B5C8E50BFAB66887B55 |
| Key |
Value |
| MD5 | 37F92897BB6B49889FD589E9E3150C2F |
| PackageArch | sparcv9 |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | Fedora Project |
| PackageName | iverilog |
| PackageRelease | 6.fc12 |
| PackageVersion | 0.9.20090423 |
| SHA-1 | 22A6FE08D7FA5D5F9096234A350AD14696C95A7F |
| SHA-256 | 3C5D6740994B128B5300DD15847F7700C66A5CF338A99A33E77267ABF798B048 |
| Key |
Value |
| FileSize | 1115122 |
| MD5 | D5098B280D6254AC35115B9B4E2959E6 |
| PackageDescription | Icarus verilog compiler
Icarus Verilog is intended to compile all of the Verilog HDL as
described in the IEEE-1364 standard. It is not quite there
yet. It does currently handle a mix of structural and behavioral
constructs.
.
The compiler can target either simulation, or netlist (EDIF). |
| PackageMaintainer | Debian Electronics Team <pkg-electronics-devel@lists.alioth.debian.org> |
| PackageName | iverilog |
| PackageSection | electronics |
| PackageVersion | 0.9.7-1 |
| SHA-1 | 259BB17CC425085C646C51B98AC8F87601E1156E |
| SHA-256 | 7A120386597C96B56B7B42BB7536B005BC96F3AE2699D9DA332737FEE25E6C64 |
| Key |
Value |
| MD5 | 5AFB89CC61D778BF7E6A4651115D9024 |
| PackageArch | s390x |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | Fedora Project |
| PackageName | iverilog |
| PackageRelease | 2.fc15 |
| PackageVersion | 0.9.20100928 |
| SHA-1 | 2901CD4F11EED288A234F7CE6B5FD24A8566CD78 |
| SHA-256 | 215D5B7D93E74ACCF5C3CF3128AE30DAA70ED049A21D4D0F061F5AB30E4021AF |
| Key |
Value |
| MD5 | D761810C48190F948E4ED35D10FDCA9F |
| PackageArch | ppc64 |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | Fedora Project |
| PackageName | iverilog |
| PackageRelease | 5.fc22 |
| PackageVersion | 0.9.20120609 |
| SHA-1 | 2DFE66F49EB2A1F785B17FB169D27AE30E3B0738 |
| SHA-256 | 9F75E2C4C58C5CF4AEF273A10B1B0380012E866C8064C04D530D1A32D6138846 |
| Key |
Value |
| MD5 | 79A0274B3466AE47F155AF378F777BAD |
| PackageArch | ppc64 |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | Fedora Project |
| PackageName | iverilog |
| PackageRelease | 5.fc21 |
| PackageVersion | 0.9.20120609 |
| SHA-1 | 2E09A9867B1894E1603C813580564DA3AE2E5F81 |
| SHA-256 | C0AB7B36E6E03FE8975BC53CE1022D880CC1E0778769503AB52956993313DF2D |
| Key |
Value |
| MD5 | 7BC15A6F49C9A6E9944D994BC8F67C31 |
| PackageArch | armv5tel |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | Fedora Project |
| PackageName | iverilog |
| PackageRelease | 3.fc17 |
| PackageVersion | 0.9.20111101 |
| SHA-1 | 2FCED5E2E146D082D88636381B960F3B1247EFCA |
| SHA-256 | 11C979738547E80121BDE1124766368BA61CD71584DD929AF048DD36FFD87941 |