Parents (Total: 9)
The searched file hash is included in 9 parent files which include package known and seen by metalookup. A sample is included below:
| Key |
Value |
| MD5 | CF37B0DC9A25BEE4EB23D9FDD885B189 |
| PackageArch | armv7hl |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard and supports a subset of the IEEE-1800
standard. |
| PackageMaintainer | umeabot <umeabot> |
| PackageName | iverilog |
| PackageRelease | 2.mga9 |
| PackageVersion | 11.0 |
| SHA-1 | CCC255F21BF9405856AAE910C610A4711B12B19D |
| SHA-256 | 7CB587B450BC30918FE4B68EB707298E04351F5D84FD655BFCA84F2405A91574 |
| Key |
Value |
| MD5 | 29F2F9D412EDDD3D917A4FBECDD6951F |
| PackageArch | armv7hl |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | Fedora Project |
| PackageName | iverilog |
| PackageRelease | 4.fc33 |
| PackageVersion | 10.3 |
| SHA-1 | DDA94A6BF471ED8E1008465158F5D896C12D14B0 |
| SHA-256 | 1C917DF5680E7B8DAA6D353AA3E33C94A5A01C2036EE0370A3800752E4F759B1 |
| Key |
Value |
| MD5 | 9FF5DCB6B486BA40BD830F49D381B5F4 |
| PackageArch | armv7hl |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard and supports a subset of the IEEE-1800
standard. |
| PackageMaintainer | martinw <martinw> |
| PackageName | iverilog |
| PackageRelease | 1.mga8 |
| PackageVersion | 11.0 |
| SHA-1 | 516DCDCAB94E4C4B175381A87EFA0EC057288FB1 |
| SHA-256 | 181D5D5F12041D84033FD93997D2EA51C7EC3296B4A5737AA6468BBE5D30D5C6 |
| Key |
Value |
| MD5 | 3B28FF69699AD773E0B8935A5AEF2539 |
| PackageArch | i586 |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard and supports a subset of the IEEE-1800
standard. |
| PackageMaintainer | martinw <martinw> |
| PackageName | iverilog |
| PackageRelease | 1.mga8 |
| PackageVersion | 11.0 |
| SHA-1 | FFD9F2592F54F8C21550357AD17FA91A3D7FC8F9 |
| SHA-256 | 993E61E40FD45C268F2E01E1FB29C94246A5C4D602E8AC6739281B7F75DD1F31 |
| Key |
Value |
| MD5 | C0116B97A1FE5F29C62A45BE334B0D48 |
| PackageArch | armv7hl |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | Fedora Project |
| PackageName | iverilog |
| PackageRelease | 1.fc32 |
| PackageVersion | 10.3 |
| SHA-1 | 947B4DD5736218746A8EB03FAFC110679C7A4DF8 |
| SHA-256 | BD292BBD2AA7F038CB32E0CAD9624321F15489503A558C86F6D09304836D2970 |
| Key |
Value |
| MD5 | 134653E30781DBBD20DC5653401DDD6D |
| PackageArch | armv7hl |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | umeabot <umeabot> |
| PackageName | iverilog |
| PackageRelease | 2.mga7 |
| PackageVersion | 10.2 |
| SHA-1 | CD15B81C296353CF436E6CA2E2B2840D2347A3FE |
| SHA-256 | 2034A67DE09AB5FA94F872B163E016CF7BA8D2CDAB7F4B024D90152744A7213C |
| Key |
Value |
| MD5 | 823F6DB8ACFD4D2D0A3E844E3F041E6C |
| PackageArch | i586 |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | umeabot <umeabot> |
| PackageName | iverilog |
| PackageRelease | 2.mga7 |
| PackageVersion | 10.2 |
| SHA-1 | 3EB1C0837D70FC6E47DCAB21EC274DB64C6E1552 |
| SHA-256 | FA8954CE4D486DF1FE9FC741447ED82887068ECA72D7A5D51EDF90C72E7CEE7A |
| Key |
Value |
| MD5 | BCF39C1934E6EEAB48B834E3EA0E9D4F |
| PackageArch | armv7hl |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. |
| PackageMaintainer | Fedora Project |
| PackageName | iverilog |
| PackageRelease | 2.fc34 |
| PackageVersion | 11.0 |
| SHA-1 | 3A4E4FBD7BC70EBB930DD55B9DF9F25E6C075F26 |
| SHA-256 | CD534261A409ADDE7F28B814914E165425BBDF6BCE421B883AA008501DFC1965 |
| Key |
Value |
| MD5 | E8AB98EE8F8C854A953E0C95D9DB1634 |
| PackageArch | i586 |
| PackageDescription | Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard and supports a subset of the IEEE-1800
standard. |
| PackageMaintainer | umeabot <umeabot> |
| PackageName | iverilog |
| PackageRelease | 2.mga9 |
| PackageVersion | 11.0 |
| SHA-1 | 0A33F7BC7AD7C35AE4104C75CC476D89FAC50096 |
| SHA-256 | 41425B53D2FFAF8C934CE2CF777CB901E96A94779511504B5A15C2C0450E5C22 |